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ADN2865,pdf,datasheet

 Continuous Rate 12.3Mb/s to 2.7Gb/s Cloc
  • 软件大小:125KB
  • 更新日期:2009/9/19
  • 软件语言:简体中文
  • 软件类别:机械电子
  • 软件授权:共享软件
  • 软件官网:
  • 适用平台:Vista, Win2003, WinXP, Win2000, NT

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    TheADN2865providesthereceiverfunctionsof。

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    The ADN2865 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 Mb/s to 2.7 Gb/s. An integrated deserialiser supports 8 bit parallel transfer to an FPGA or digital ASIC. The recovered clock can simultaneously serialize data supplied in an 8 bit parallel format.

    The ADN2865 automatically locks to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are exceeded, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted.

    This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power fiber optic receiver.

    The ADN2865 have many optional features available via an I2C interface, e.g. the user can read back the data rate that the ADN2865 is locked on to, or the user can set the device to only lock to one particular data rate if provisioning of data rates is required.

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